Hi all, my application has 32 x 16bit incoming video channels. This is a fifo that has 1 slave axi stream interface and 1 master axi stream interface. Axi4stream interconnect provides buffering, data steering. When configured to upsize the data width by a factor of 2, there are only 4 burst buffers implemented in the fifo. I have configured the fifo for packet mode, and size equal to 2048. Hello everyone, i am using a axi4 stream data fifo on a zynq7000 7z020 to store data incoming on a stream from a custom module before reading it with an axi dma. The valid signal is pulled low only when there is no data available to be read. Download the xilinx documentation navigator from the design tools tab. It seems that the axi4stream fifo would be ideal as it converts from axistream to axi4 and i could connect it directly to the axi interconnect for dma processing. The principal operation of this core allows the write or read of data packets to or from a device without any concern over the axi streaming interface. Download the xilinx documentation navigator from the design tools tab on the.
I was hoping to use an axi fifo of sorts to buffer 512bits per clock cycle. Axi4axi3 write address channel fifo interface signals. When configured to upsize by any larger ratio, there will be 8 buffers implemented. Hi, in my design i am using axi4 stream data fifo as a part of logic for averaging components over two lines two video lines. The fifo is always implemented with a depth of 512 single bram block, as viewed on the wider mi interface. The core can be used to interface to the axi ethernet without the need to use dma. For axi4, the fifo data width matches the axi4stream. Before beginning an axi design, you need to download, read, and understand the. It is not the axi4 stream fifo, which is a mm2s type device.